This application claims the benefit of a Japanese Patent Application No.2000-207448 filed Jul. 7, 2000, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to encoding units and decoding units, and more particularly to an encoding unit and a decoding unit which use a run length limited (RLL) code and an error correction code (ECC).
2. Description of the Related Art
In a conventional magnetic recording and/or reproducing apparatus such as a magnetic disk unit, the RLL code is used to facilitate extraction of a clock component or adjusting synchronization, and the ECC such as a Reed Solomon code is used for the error correction, when recording information on and reproducing information from a magnetic recording medium. Hence, a high-density information recording and reproduction can be carried out with a high reliability.
FIG. 1 is a system block diagram showing a first example of recording and reproducing systems of the conventional magnetic recording and reproducing apparatus.
In FIG. 1, a recording system generally includes a scrambler 1, an ECC encoder 2, a RLL encoder 3, a parity encoder 4, and a known recording means (not shown) for recording information on a recording medium 5. On the other hand, a reproducing system generally includes a known reproducing means (not shown) for reproducing the information from the recording medium 5, an equalizer 6, a most likelihood detector 7, a RLL decoder 8, an ECC decoder 9, and a descrambler 10.
The information which is to be recorded on the recording medium 5 is scrambled in the scrambler 1, and is added with a parity byte in the ECC encoder 2. The RLL encoder 3 subjects the information which is scrambled and added with the parity byte to a RLL encoding. The parity encoder 4 subjects a parity byte portion to a RLL encoding. Hence, encoded information is recorded on the recording medium 5 by the recording means. On the other hand, the encoded information which is reproduced from the recording medium 5 by the reproducing means is supplied to the most likelihood detector 7 via the equalizer 6, and is converted into the RLL code by a most likelihood detection. The RLL decoder 8 subjects the RLL code output from the most likelihood detector 7 to a RLL decoding. The ECC decoder 9 carries out an error correction with respect to the RLL decoded information. The descrambler 10 descrambles the decoded and error-corrected information, so as to reproduce the recorded information.
However, according to this first example, the RLL code word itself becomes long when the code efficiency of the RLL code is increased. Hence, when an error exists in a portion of the RLL code, the error is propagated over a long range by the decoding process, thereby deteriorating a burst error correcting performance of the ECC.
FIG. 2 is a system block diagram showing a second example of the recording and reproducing systems of the conventional magnetic recording and reproducing apparatus, which has been proposed to eliminate the problems of the first example described above. In FIG. 2, the illustration of the recording means, the recording medium and the reproducing means is omitted for the sake of convenience. In this second example, the ECC encoder and the RLL encoder of the recording system are provided in a reverse order to that of the first example, and the RLL decoder and the ECC decoder of the reproducing system are provided in a reverse order to that of the first example.
In FIG. 2, the recording system includes a scrambler 11, a RLL1 encoder 12, and an ECC encoder 13, where RLL1 indicates a first RLL encoding. On the other hand, the reproducing system includes an ECC decoder 15, a RLL1 decoder 16, and a descrambler 17.
The RLL1 encoder 12 subjects the information which is scrambled in the scrambler 11 to a RLL1 encoding, and the ECC encoder 13 encodes the RLL1-encoded information by ECC. More particularly, the ECC encoder 13 includes a RLL2 encoder 131, and subjects the parity byte to a RLL2 encoding and adds the RLL2-encoded information to the RLL1-encoded information, where RLL2 indicates a second RLL encoding, because the parity byte which is to be added does not satisfy the rules of the RLL1 code. The RLL2-encoded RLL1-encoded information is recorded on the recording medium by the recording means, and the recorded information is reproduced from the recording medium by the reproducing means.
The reproduced encoded information is supplied to the ECC decoder 15. The ECC decoder 15 includes a RLL2 decoder 151, and subjects the RLL2-encoded parity byte to a RLL2 decoding, so as to correct the error of the RLL1-encoded information. The RLL1 decoder 16 subjects the error-corrected RLL1 encoded data to a RLL1 decoding, and the descrambler 17 descrambles the decoded information so as to reproduce the recorded information.
However, when the RLL-encoded information is encoded by the ECC in the second example, the added parity byte does not satisfy the rules of the RLL code. For this reason, it is necessary to further carry out the RLL encoding with respect to the parity byte, and it is thus necessary to employ a complicated format using double codes. As a result, it takes time to carry out the correction process using the ECC in the reproducing system, thereby increasing the number of buffer circuits which are required to absorb delays and also increasing the scale of the circuit.
Accordingly, it is a general object of the present invention to provide a novel and useful encoding unit and decoding unit, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide an encoding unit and a decoding unit which can suppress error propagation and improve error correcting performance of ECC, without increasing the scale of the circuit.
Still another object of the present invention is to provide an encoding unit comprising separating means for separating a RLL code into a restricting portion corresponding to a basic code and a non-restricting portion corresponding to information bits, first encoding means for adding an error correction code to the restricting portion and carrying out a RLL encoding, second encoding means for adding an error correction code to the non-restricting portion, and interleaving means for interleaving outputs of the first and second encoding means, and outputting encoded information. According to the encoding unit of the present invention, it is possible to suppress error propagation and improve error correcting performance of ECC, without increasing the scale of the circuit.
A further object of the present invention is to provide a decoding unit for decoding encoded information in which first and second information are interleaved, where the first information is subjected to a RLL encoding by adding a parity to a restricting portion which corresponds to a basic code of a RLL code and the second information is added with an error correction code to a non-restricting portion which corresponds to information bits of the RLL code, comprising separating means for separating the encoded information into the first and second information, first decoding means for subjecting the separated first information to a RLL decoding and an error correction, second decoding means for subjecting the separated second information to an error correction, and interleaving means for interleaving outputs of the first and second decoding means, and outputting decoded information. According to the decoding unit of the present invention, it is possible to suppress error propagation and improve error correcting performance of ECC, without increasing the scale of the circuit.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.